Interactive HDL Simulator & Timing Analyzer
Helping you make the leap in to VHDL and Verilog
By Donna Mitchell
Have you moved to an HDL language? Most engineers are just learning Verilog and VHDL, and after years of experience designing digital
circuits they are reduced to fighting with their HDL compiler just to get simple combinatorial logic and a few flip-flops to simulate for the first time. There is nothing more frustrating than knowing exactly how your circuit works, yet being unable to make even the simplest parts simulate properly. Relief from HDL frustration has arrived with the advent of WaveFormer Pro v4.0, a new type of timing analysis tool which combines a timing diagram analyzer with an Interactive HDL simulator (See Figure 1).
Figure1: Picture shows WaveFormer Pro's Logic Wizard entry in the Signal Properties Window. The Report window is displaying the complete Verilog model for the circuit described in the timing diagram. Min/max timing analysis is controlled by times in the Parameter Table. Evaluation version available at http://www.syncad.com
WaveFormer Pro's Interactive HDL Simulator represents a new way to perform simulation and timing analysis. WaveFormer is different from regular
simulators in that a complete circuit or schematic is not needed in order to start the simulation process. Your initial design ideas can be immediately simulated as soon as you enter the design information. Some of the advantages that you get from an interactive HDL simulation environment are:
No previous HDL training required Interactive HDL Simulation bridges the gap between knowing how to design digital circuits and how to express them in an HDL language. With WaveFormer, users enter design information
in a familiar way: Boolean equations, register and latch elements, and graphical test vectors. This information is automatically converted to HDL code and simulated whenever an input waveform or design equation changes. Once design information is entered, users can view the HDL code generated for each latch or equation. Users can quickly gain an understanding of the operation of HDL statements, even in more complex models that support worst case (min/max) timing simulation.
Interactive HDL Simulation
speeds up design entry and timing analysis In the past, engineers have used timing diagrams to perform timing checks early in the design cycle. However, manually creating timing diagrams is a tedious and error prone process. Timing diagram editors eliminated some of the problems associated with creating timing diagrams by easing the process of editing the diagrams and automatically calculating delay paths and setup/hold margins. However, even using timing diagram editors, it still takes a lot of time to
enter the first diagram, draw all the signals, calculate the results of Boolean logic, and account for the effects of registered signals.
WaveFormer Pro v4.0 overcomes these difficulties by changing the way timing diagrams are entered and updated. WaveFormer Pro continuously simulates Boolean logic and registered signals and displays the results in the timing diagram editor window. Any change to the design information such as moving an edge on an input signal or changing a delay in a logic equation
automatically triggers a re-simulation, providing instant feedback on the impact of changes on system functionality and performance.
Min/max/worst-case timing and reconvergent fanout analysis WaveFormer Pro generates HDL models that support min, max, and worst case (min/max) timing analysis. Engineers rarely get a chance to simulate worst case timing because most HDL models do not support the computational overhead and most gate-level simulators cannot perform this type of simulation. Worst case simulation
enables designers to check for race conditions that can occur because of component timing tolerances. Worst case simulation is especially beneficial when designing interfaces between systems (e.g. "glue" logic using PLDs, FPGAs, or ASICs) as these designs commonly require asynchronous handshaking protocols with critical timing requirements.
WaveFormer also supports common delay uncertainty removal (sometimes referred to as reconvergent fanout analysis). Delay uncertainty is the difference
between the max time and the min time of a gate delay in a design. Uncertainty on a single delay that cascades down two different signal paths can be removed when computing relative times between signal transitions on those two paths as the delay will be the same for both paths. Removal of this uncertainty when checking timing constraints (setup and hold time slack) corrects overly pessimistic slack calculations that can mislead a designer into thinking a design doesnít meet its timing requirements when it does.
Summary SynaptiCAD's WaveFormer Pro v4.0 with Interactive HDL Simulation represents a new way to perform simulation and timing analysis. With WaveFormer you enter the design information in a familiar way: Boolean equations, register and latch elements, and graphical test vectors. WaveFormer converts this design information into HDL models that support true min/max timing and then simulates the models. Users can view and edit the generated code. Models and test benches can be exported and used with
external VHDL and Verilog simulators.
Donna Mitchell (donna@syncad.com) is the vice president of Marketing at SynaptiCAD (Blacksburg, Va.)
